In some storage systems, the execution of storage commands may result in temporal high power or current consumption. Methods for limiting power consumption in storage systems are known in the art. For example, U.S. Pat. No. 8,090,898, whose disclosure is incorporated herein by reference, describes a nonvolatile memory system that has a controller chip connected to a memory medium and to several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused by the operation and thereby improve the stability of the system.
U.S. Patent Application Publication 2013/0301372, whose disclosure is incorporated herein by reference, describes a power management method that includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die. After receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation. Execution of second high power operation is delayed until completion of the first high power operation.
U.S. Pat. No. 8,645,723, whose disclosure is incorporated herein by reference, describes systems and methods for controlling power consumption in a system having multiple NVM dies, using asynchronous management of access requests. An arbiter of the system receives multiple requests to draw current, each request may be associated with a different NVM die. In some embodiments, the arbiter serves the requests based on their time of arrival using, for example, a first-in, first-out serving scheme. In other embodiments, the arbiter can serve multiple requests simultaneously, if not exceeding a power budget.